Nonvolatile semiconductor storage device and method for operating same

ABSTRACT

A nonvolatile semiconductor memory device for suppressing a current consumption caused by a transient current because of the potential change of the bit and word lines at the time of shifting between the programming, reading, and erasing actions in a highly integrated memory cell array is provided. A memory cell ( 1 ) array comprises two-terminal memory cells each having a variable resistance element whose resistance value reversibly changes by pulse application are arranged in a row and column directions, wherein the memory cells in a row are connected at one end to common word lines (WL 1  to WLn), the memory cells in a column are connected at the other end to common bit lines (BL 1  to BLm), and a common unselected voltage V WE /2 is applied to both unselected word and bit lines not connected to the selected memory cell during the reading, programming, and erasing actions for the selected memory cell.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Reissue of U.S. Pat. No. 7,978,495 (previouslyU.S. patent application Ser. No. 11/883,552, filed Jan. 5, 2006), whichis a National Phase filing under 35 U.S.C. §371 of InternationalApplication No. PCT/JP2006/300041 filed on Jan. 5, 2006, and whichclaims priority to Japanese Patent Application No. 2005-025935 filed onFeb. 2, 2005.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device having amemory cell array in which a plurality of two-terminal memory cellscomprising a variable resistance element having a resistance valuereversibly changed by electric pulse application and storing informationby the change of the electric resistance are arranged in a row directionand a column direction, and more particularly, to a voltage controltechnique for bit lines and word lines in each memory action of reading,programming and erasing actions.

BACKGROUND ART

Recently, as a next-generation NVRAM (Nonvolatile Random Access Memory)capable of implementing high-speed action to be replaced with a flashmemory, various kinds of device structures such as a FeRAM(Ferroelectric RAM), a MRAM (Magnetic RAM), and an OUM (Ovonic UnifiedMemory) have been competitively developed in view of implementing highperformance, high reliability, low cost, and process consistency.

In addition, based on these existing technique, a method of changingelectric resistance reversely by applying an electric pulse to theperovskite material known for a super colossal magnetoresistance effectis disclosed by Shangquing Liu, Alex Ignatiev et al. in University ofHouston, in the following patent document 1 and non-patent document 1.This is extremely innovative because resistance change over severaldigits can be implemented at a room temperature without applying anelectric field while using the perovskite material known for the supercolossal magnetoresistance effect. A resistance nonvolatile RRAM(Resistance Random Access Memory) using a variable resistance elementand employing this phenomenon is extremely low in power consumptionbecause it does not need a magnetic field at all unlike the MRAM andeasy to miniaturize and highly integrate and has a considerably largedynamic range of the resistance change as compared with the MRAM, sothat it has excellent characteristics such that multilevel storage canbe implemented. The basic structure in an actual device is considerablysimple such that a lower electrode material, a provskite-type metaloxide, and an upper electrode material are laminated in this order on asubstrate in the vertical direction. In addition, according to theelement structure illustrated in patent document 1, the lower electrodematerial is yttrium-barium-copper oxide YBa₂Cu₃O₇ (YBCO) film depositedon a single-crystal substrate of lanthanum-aluminum oxide LaAlO₃ (LAO),the perovskite-type metal oxide is a crystallinepraseodymium-calcium-manganese oxide Pr_(1-x)Ca_(x)MnO₃ (PCMO) film, andthe upper electrode material is an Ag film deposited by sputtering.According to the action of the memory element, it is reported that theresistance can be reversibly changed by applying positive and negativevoltage pulse of 51 volts between the upper and lower electrodes. Thenovel nonvolatile semiconductor memory device is implemented by readingthe resistance value in this reversible resistance changing action(referred to as the “switching action” occasionally hereinafter).

A nonvolatile semiconductor memory device is constituted such that amemory cell array in which memory cells comprising a variable resistanceelement consisting of the PCMO film and the like and storing informationby the change of the electric resistance of the variable resistanceelement are arranged in a row direction and column direction like amatrix is formed, and circuits for controlling data programming, erasingand reading for each memory cell in the memory cell array are disposedaround the memory cell array.

As the constitution of the memory cell comprising the variableresistance element, a two-terminal memory cell comprising only thevariable resistance element is called a 1R type memory cell.

FIG. 1 shows one constitution example of a large-capacity nonvolatilesemiconductor memory device in which a memory cell array 1 has 1R typememory cells as components. As shown in FIG. 2, a 1R type memory cell 10comprises a single variable resistance element and the memory cells 10are arranged in a matrix shape to constitute the memory cell array 1,which is similar to that disclosed in the following patent document 2,for example. More specifically, the memory cell array 1 is constitutedsuch that m×n memory cells 10 are disposed at intersections of m (BL1 toBLm) bit lines extending in the column direction and n (WL1 to WLn) wordlines extending in the row direction. According to each memory cell 10,the upper electrode of the variable resistance element is connected tothe word line, and the lower electrode of the variable resistanceelement is connected to the bit line. In addition, the relation betweenthe upper electrode and the lower electrode of the variable resistanceelement may be reversed such that the lower electrode of the variableresistance element is connected to the word line and the upper electrodeof the variable resistance element is connected to the bit line.

As shown in FIG. 1, according to the nonvolatile semiconductor memorydevice comprising the memory cell array 1 comprising the 1R type memorycells 10, a specific memory cell in the memory cell array 1corresponding to an address input inputted to a control circuit 6a froman address line 4 is selected by a bit line decoder 2 and a word linedecoder 3, and each action of data programming, erasing and reading iscarried out so that data is stored in the selected memory cell and read.The data input/output with an external device (not shown) is performedthrough a data line 5.

The word line decoder 3 selects the word line of the memory cell array 1according to a signal inputted to the address line 4. The bit linedecoder 2 selects the bit line of the memory cell array 1 according toan address signal inputted to the address line 4. The control circuit 6acontrols each action of data programming, erasing and reading of thememory cell array 1. The control circuit 6a controls the word linedecoder 3, the bit line decoder 2, a voltage switch circuit 8a, andprogramming, erasing and reading action of the memory cell array 1,based on the address signal inputted from the address line 4, a datainput (at the time of programming) inputted from a data line 5, and acontrol input signal inputted from a control signal line 7. In theexample shown in FIG. 1, the control circuit 6a is provided with afunction as a general address buffer circuit, data input/output buffercircuit, and control input buffer circuit though they are not shown.

The voltage switch circuit 8a switches each voltage of the word line andbit line required for the reading action, programming action and erasingaction of the memory cell array 1 according to an action mode andsupplies it to the memory cell array 1. Here, reference character Vccdesignates a power supply voltage of the nonvolatile semiconductormemory device of the present invention, reference character Vssdesignates the ground voltage, reference character Vpp designates aprogramming or erasing voltage, and reference character V1 designates areading voltage. In addition, the data reading is carried out from thememory cell array 1 through the bit line decoder 2 and the readingcircuit 9. The reading circuit 9 determines the state of the data andtransfers its result to the control circuit 6a to be outputted to thedata line 5.

In the memory cell array 1 comprising the 1R type memory cells 10, areading current flowing in the memory cell selected by the row or columnis detected as the reading current of the memory cell to be read.Although the reading current flows in other memory cells of the memorycell array 1 comprising the 1R type memory cells 10, there areadvantages that the memory cell structure is simple and the memory cellarea and memory cell array area are small.

A conventional example of an electric pulse applying process to eachpart in the memory cell array 1 comprising the 1R type memory cells 10at the time of data reading action will be described with reference toFIGS. 2 and 3. When the data in the selected memory cell is read, theselected word line connected to the selected memory cell is kept at Vssand the reading voltage V1 is applied to unselected word lines and allthe bit lines during a reading period Tr. During the reading period Tr,since the voltage difference of the reading voltage V1 is generatedbetween the selected word line and all the bit lines, a reading currentcorresponding to its electric resistance, that is, the memory stateflows in the variable resistance element of the selected memory cell, sothat the data stored in the selected memory cell can be read. In thiscase, since the reading current corresponding to the memory state of theselected memory cell connected to the selected word line flows in eachbit line, when the reading current flowing in a certain selected bitline is selectively read on the bit line side, the data in the specificselected memory cell can be read. Here, the relation of the bit line andthe word line may be switched such that the reading current flowing ineach word line is selectively read on the word line side.

FIG. 5 shows a conventional example of an electric pulse applying methodto each word line and each bit line at the time of data reading,programming or erasing action in the memory cell array 1 comprising the1R type memory cells 10, and FIG. 4 shows one example of a nonvolatilesemiconductor memory device for controlling it. The example of theelectric pulse applying method to each word line and each bit line shownin FIG. 5 is similar to that disclosed in a non-patent document 2. Whendata is read, programmed or erased in the selected memory cell, theground voltage Vss is applied to one of the selected word line and theselected bit line connected to the selected memory cell and a voltage Varequired for implementing the reading action, programming action orerasing action is applied to the other of the selected word line or theselected bit line. The voltage of all unselected word lines and allunselected bit lines is set to the half of the voltage Va required forimplementing the reading, programming or erasing action, that is, Va/2.

The nonvolatile semiconductor memory device having the constitutionshown in FIG. 4 is basically the same as that of the conventionalnonvolatile semiconductor memory device shown in FIG. 1. It is differentfrom the conventional non-volatile semiconductor memory device shown inFIG. 1 in the voltage supplied from the voltage switch circuit 8b toeach word line and each bit line of the memory cell array 1 and acontrol method of that voltage. According to the constitution shown inFIG. 4, the voltage switch circuit 8b applies the voltages Va and Va/2to a certain bit line and word line in addition to the voltage Vcc andVss.

FIG. 7 shows another conventional example of an electric pulse applyingmethod to each word line and each bit line at the time of data reading,programming or erasing action in a memory cell array 1 comprising 1Rtype memory cells 10, and FIG. 6 shows one example of a nonvolatilesemiconductor memory device for controlling it. The example of theelectric pulse applying method to each word line and each bit line shownin FIG. 7 is similar to that disclosed in the non-patent document 2.When data is read, programmed or erased for the selected memory cell,the ground voltage Vss is applied to one of the selected word line andthe selected bit line connected to the selected memory cell and avoltage Va required for implementing the reading action, programmingaction or erasing action is applied to the other of the selected wordline or the selected bit line. A voltage of two thirds of the voltage Varequired for the reading, programming or erasing action, that is, 2Va/3is applied to all unselected lines on the side to which the groundvoltage Vss is applied, among the word lines and bit lines. A voltage ofone third of the voltage Va, that is, Va/3 is applied to all unselectedlines on the side to which the voltage Va is applied, among the wordlines and bit lines.

The nonvolatile semiconductor memory device having the constitutionshown in FIG. 6 is basically the same as that of the conventionalnonvolatile semiconductor memory device shown in FIG. 1. It is differentfrom the conventional non-volatile semiconductor memory device shown inFIG. 1 in the voltage supplied from a voltage switch circuit 8c to eachword line and each bit line of the memory cell array 1 and a controlmethod of that voltage. According to the constitution shown in FIG. 6,the voltage switch circuit 8c applies the voltages Va, 2Va/3 and Va/3 toa certain bit line and word line in addition to the voltages Vcc andVss.

The variable resistance element constituting the 1R type memory cellincludes a phase-change memory element in which a resistance value ischanged by the change in crystalline/amorphous state of chalcogenidecompound, a MRAM element using a resistance change by a tunnel magneticresistance effect, a memory element of a polymer ferroelectric RAM(PERAM) in which a resistance element is formed of a conductive polymer,a RRAM element causing a resistance change by an electric pulseapplication and the like.

-   Patent document 1: U.S. Pat. No. 6,204,139-   Patent document 2: Japanese Unexamined Patent Publication No.    2002-8369-   Non-patent document 1: Liu, S. Q. et al. “Electric-pulse-induced    reversible Resistance change effect in magnetoresistive films”,    Applied Physics Letter, Vol. 76, pp. 2749-2751, in 2000.

DISCLOSURE OF THE INVENTION Problem to be Solved by the Invention

In order to implement the reading, programming or erasing action of datafor a memory cell array constituting 1R type memory cells, it isnecessary to apply a predetermined voltage to each of a selected wordline, a selected bit line, unselected word lines and unselected bitlines. When each word line and each bit line are brought to thepredetermined voltage level, a transient current due to charging anddischarging of parasitic capacity in the word line and bit line isgenerated. When each action mode of the reading, programming and erasingactions is moved to another action mode, the transient current due tothe above charging and discharging of the parasitic capacity flows,causing current consumption to be increased in a nonvolatilesemiconductor memory device.

Using the electric pulse applying method (refer to FIG. 5) to each wordline and each bit line disclosed in the non-patent document 2, a casewhere data 0 is read from the selected memory cell storing the data 0and then different data 1 is programmed will be described. At the timeof reading, either the selected word line or the selected bit lineconnected to the selected memory cell is set at the ground voltage Vss,and the other of the selected word line or the selected bit line is setat a reading voltage Vread required for the reading action. The voltageof the all the unselected word lines and all the unselected bit lines isset to the half of the reading voltage Vread, that is, Vread/2. At thetime of programming, either the selected word line or the selected bitline connected to the selected memory cell is set at the ground voltageVss, and the other of the selected word line or the selected bit line isset at a programming voltage Vwrite required for the programming action.The voltage of the all the unselected word lines and all the unselectedbit lines is set to the half of the programming voltage Vwrite, that is,Vwrite/2. At the time of shifting from the reading action to theprogramming action, when it is assumed that the selected memory cell atthe time of the reading is the same as the selected memory cell at thetime of programming for simplifying the description, the voltage of allthe unselected word lines and all the unselected bit lines is increasedfrom the Vread/2 at the time of reading to the Vwrite/2 at the time ofprogramming. Namely, a voltage change of (Vwrite−Vread)/2 is generatedin the signal lines of the total number of the unselected bit lines andthe unselected word lines. Although one of the voltages of the selectedbit line and the selected word line is the ground voltage Vss and it isnot changed at the time of reading and programming, the other one of theselected bit line or the selected word line is increased from Vread toVwrite. When the voltage of the bit line and word line other than oneselected bit line or selected word line set at the ground voltage Vss ischanged at the time of shifting from the reading action to theprogramming action, parasitic capacity is charged in the word line andbit line, so that the current consumption at the time of the action isincreased.

In addition, when the reading is performed after the programming,although the direction is opposite to the above, the voltage of all theunselected word lines and all the unselected bit lines is lowered fromthe Vwrite/2 at the time of programming to the Vread/2 at the time ofreading, so that the parasitic capacity is discharged in the word lineand bit line and the current consumption at the time of the action isincreased.

In each action of the reading, programming and erasing action, whenspecific bit line and word line are selected from all the bit lines andword lines, an action preparing period (precharging period) is providedjust before shifting to each action and after all the bit lines and wordlines are set in an unselected state once, the specific bit line andword line are shifted from the unselected states to selected states. Inthis case, since only the voltage of the selected word line and selectedbit line is changed in the same action mode, the current consumption canbe prevented from being increased. However, even in the case where theprecharging period is provided just before shifting to each action,since the voltage level of the unselected word lines and the unselectedbit lines is different between the reading action, programming actionand erasing action similar to the case where the reading action,programming action or the erasing action is directly shifted, the sameproblem is generated.

The present invention was made in view of the above problems and it isan object of the present invention to provide a nonvolatilesemiconductor memory device capable of controlling a current consumptionincreased by a transient current because of the potential change of thebit line and word line at the time of shifting between the action modesof reading, programming and erasing, in a highly integrated memory cellarray, and its operating method.

Means for Solving the Problems

A nonvolatile semiconductor memory device according to the presentinvention to attain the above object is characterized by comprising amemory cell array comprising two-terminal memory cells each comprising avariable resistance element having a resistance value reversibly changedby electric pulse application, and arranged in a row direction andcolumn direction such that one end of each memory cell in the same rowis connected to a common word line and the other end of each memory cellin the same column is connected to a common bit line, a memory cellselecting circuit selecting the memory cell from the memory cell arrayby the row, column or memory cell, a voltage switch circuit applying avoltage required for each of a plurality of memory actions includingreading, programming and erasing in the memory cell selected by thememory cell selecting circuit, to the selected word line and theselected bit line connected to the selected memory cell and to theunselected word lines and the unselected bit lines other than the aboveselected word line and selected bit line among the word lines and thebit lines, according to the memory action, and a reading circuit readingthe information stored in the memory cell to be read in the selectedmemory cells by detecting the amount of a reading current flowingaccording to the resistance value of the variable resistance element inthe memory cell to be read, wherein the voltage switch circuit applies acommon unselect voltage to both unselected word lines and unselected bitlines during each action period for the reading, programming and erasingactions.

In addition, the nonvolatile semiconductor memory device according tothe present invention is characterized in that the voltage switchcircuit applies a common unselect voltage to one of the unselected wordlines and the unselected bit lines at least in each action period forthe reading action and the programming action, and applies the commonunselect voltage to the other of the unselected word lines and theunselected bit lines at least in each action period for the readingaction and the erasing action.

Furthermore, the nonvolatile semiconductor memory device according tothe present invention is characterized in that the voltage switchcircuit applies the unselect voltage to at least the unselected wordlines and the unselected bit lines in each action preparing period justbefore each memory action of the reading, programming and erasingactions.

An operating method of a nonvolatile semiconductor memory deviceaccording to the present invention to attain the above object is foroperating a nonvolatile semiconductor memory device comprising a memorycell array comprising two-terminal memory cells each comprising avariable resistance element having a resistance value reversibly changedby electric pulse application, and arranged in a row direction andcolumn direction such that one end of each memory cell in the same rowis connected to a common word line and the other end of each memory cellin the same column is connected to a common bit line, for a plurality ofmemory actions comprising a reading action, a programming action and anerasing action in a selected memory cell selected from the memory cellarray by the row, column, or memory cell, and it is characterized inthat a common unselect voltage is applied to both unselected word linesand unselected bit lines that are not connected to the selected memorycell in the word lines and the bit lines in each action period of thereading action, programming action and erasing action.

In addition, the operating method of the nonvolatile semiconductormemory device according to the present invention is characterized inthat a common unselect voltage is applied to one of the unselected wordlines and the unselected bit lines that are not connected to theselected memory cell among the word lines and bit lines at least in eachaction period of the reading action and programming action, and thecommon unselect voltage is applied to the other of the unselected wordlines and the unselected bit lines at least in each action period of thereading action and erasing action.

Furthermore, the operating method of the nonvolatile semiconductormemory device according to the present invention is characterized inthat the unselect voltage is applied to the unselected word lines andthe unselected bit lines in each action preparing period just beforeeach memory action of the reading, programming and erasing actions.

Effects of the Invention

According to the nonvolatile semiconductor memory device and theoperating method of the nonvolatile semiconductor memory device havingthe above characteristics, since the voltage applied to at least one ofthe unselected word lines and unselected bit lines is common unselectvoltage in the reading action and the programming action, or in thereading action and the erasing action, the voltage of at least one ofthe unselected word lines and the unselected bit lines is not changed atthe time of shifting between the action modes, so that at least thenumber of the word lines and bit lines causing the voltage change at thetime of shifting between the action modes can be reduced, and thetransient current caused by the charging and discharging of theparasitic capacity in each word line and each bit line can be reduced,whereby the current consumption at the time of action can be reduced.Especially, when the voltages applied to both unselected word lines andunselected bit lines are the common unselect voltage in all the actionmodes of reading, programming and erasing, the current consumptionreducing effect at the time of the action becomes more excellent.

Furthermore, even when the action preparing period (precharging period)is provided just before each action, in the case of shifting from theaction preparing period for one action mode to the action preparingperiod for another action mode or to another action mode, or in thereverse case, since the voltage of both unselected word lines andunselected bit lines is not changed, the number of the word lines andbit lines whose voltage is changed at the time of shifting between theaction modes can be considerably reduced, whereby the currentconsumption reducing effect at the time of action can become moreexcellent.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing one constitution example of aconventional nonvolatile semiconductor memory device comprising a memorycell array having 1R type memory cells;

FIG. 2 is a circuit diagram schematically showing one constitutionexample of the memory cell array having the 1R type memory cellscomprising only a variable resistance element;

FIG. 3 is a timing chart showing a conventional example of an electricpulse applying process to each word line and each bit line at the timeof reading action in the memory cell array having the 1R type memorycells;

FIG. 4 is a block diagram showing another constitution example of aconventional nonvolatile semiconductor memory device comprising a memorycell array having 1R type memory cells;

FIG. 5 is a circuit diagram showing one constitution example of a memorycell array having 1R type memory cells comprising a variable resistanceelement only and schematically showing a conventional example of anelectric pulse applying process to each word line and each bit line atthe time of each action of reading, programming and erasing,

FIG. 6 is a block diagram showing another constitution example of aconventional nonvolatile semiconductor memory device comprising a memorycell array having 1R type memory cells;

FIG. 7 is a circuit diagram showing one constitution example of a memorycell array having 1R type memory cells comprising a variable resistanceelement only and schematically showing a conventional example of anelectric pulse applying process to each word line and each bit line atthe time of each action of reading, programming and erasing;

FIG. 8 is a block diagram showing a whole schematic constitution examplein a first embodiment of a nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 9 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of programming action inthe first embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 10 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of programming action inthe first embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 11 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of erasing action in thefirst embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 12 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of erasing action in thefirst embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 13 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of reading action in thefirst embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 14 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of reading action in thefirst embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 15 is a block diagram showing a whole schematic constitutionexample in a second embodiment of a nonvolatile semiconductor memorydevice according to the present invention;

FIG. 16 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of programming action inthe second embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 17 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of programming action inthe second embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 18 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of erasing action in thesecond embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 19 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of erasing action in thesecond embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 20 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of reading action in thesecond embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 21 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of reading action in thesecond embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 22 is a block diagram showing a whole schematic constitutionexample in a third embodiment of a nonvolatile semiconductor memorydevice according to the present invention;

FIG. 23 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of programming action inthe third embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 24 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of programming action inthe third embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 25 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of erasing action in thethird embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 26 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of erasing action in thethird embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 27 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of reading action in thethird embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 28 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of reading action in thethird embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 29 is a block diagram showing a whole schematic constitutionexample in a fourth embodiment of a nonvolatile semiconductor memorydevice according to the present invention;

FIG. 30 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of programming action inthe fourth embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 31 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of programming action inthe fourth embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 32 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of erasing action in thefourth embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 33 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of erasing action in thefourth embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention;

FIG. 34 is a circuit diagram showing an electric pulse applying processto each word line and each bit line at the time of reading action in thefourth embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention; and

FIG. 35 is a timing chart showing the electric pulse applying process toeach word line and each bit line at the time of reading action in thefourth embodiment of the nonvolatile semiconductor memory deviceaccording to the present invention.

EXPLANATION OF REFERENCE CHARACTERS

-   1 Memory cell array-   2 Bit line decoder-   3 Word line decoder-   4 Address line-   5 Data line-   6a, 6b, 6c, 6d, 6e, 6f, 6g Control circuit-   7 Control signal line-   8a, 8b, 8c, 8d, 8e, 8f, 8g Voltage switch circuit-   9 Reading circuit-   10 Memory cell, Variable resistance element-   BL1 to BLm Bit line (column select line)-   WL1 to WLn Word line (row select line)-   Vcc Power supply voltage-   Vss Ground voltage-   Vpp Programming or erasing voltage-   Va Programming, erasing or reading voltage-   V_(WE) Programming voltage, erasing voltage-   V_(R) Reading voltage-   V1 _(R), V2 _(R), V3 _(R) First reading voltage-   Te Erasing action period-   Tr Reading action period-   Tw Programming action period

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of a nonvolatile semiconductor memory device and itsoperating method according to the present invention (referred to as the“device of the present invention” and “method of the present invention”occasionally hereinafter) will be described with reference to thedrawings hereinafter.

According to this embodiment, a memory cell that constitutes a memorycell array of a nonvolatile semiconductor memory device comprises avariable resistance element in which a resistance value is reversiblychanged by an electric pulse application and information is stored bythe electric resistance change. As one example of the variableresistance element, a three-layer structure RRAM element in which Ptelectrodes are provided so as to sandwich a PCMO film will be described.In addition, the present invention can be applied to any variableresistance element as long as its resistance is changed by the electricpulse application (or current application). Even when the variableresistance element is formed of a metal oxide other than the PCMO film,as long as its resistance is changed by the electric pulse application,the preset invention can be applied to it. In addition, when thevariable resistance element is formed of a transition metal oxide andthe resistance is changed by the electric pulse application, the presentinvention can be applied to it.

First Embodiment

First, a description will be made of a first embodiment in which acommon unselect voltage V_(WE)/2 is applied to unselected word lines andunselected bit lines in each memory action of programming, erasing andreading in the device of the present invention, with reference to FIGS.8 to 14.

FIG. 8 is a block diagram showing the functional constitution of thedevice of the present invention. In FIG. 8, a description will be madesuch that a common sign is allotted to a part common to that in theconventional nonvolatile semiconductor memory device. As shown in FIG.8, the device of the present invention comprises a bit line decoder 2, aword line decoder 3, a voltage switch circuit 8d, a reading circuit 9,and a control circuit 6d around a memory cell array 1 comprising 1R typememory cells arranged like a matrix as shown in FIG. 9. Basically, theconstitution is the same as that of the conventional nonvolatilesemiconductor memory device shown in FIG. 1. It is different from theconventional nonvolatile semiconductor memory device shown in FIG. 1 inthe voltages applied to each word line and each bit line of the memorycell array 1 from the voltage switch circuit 8d and the control actionof the applied voltage by the control circuit 6d.

The constitution of the memory cell array 1 is also the same as thememory cell array 1 of the conventional nonvolatile semiconductor memorydevice shown in FIG. 2. More specifically, the memory cell array 1 has astructure in which m×n memory cells 10 are positioned at intersectionsof m (BL1 to BLm) bit lines (corresponding to a column select lines)extending in a column direction and n (WL1 to WLn) word lines(corresponding to row select lines) extending in a row direction. Ineach memory cell 10, an upper electrode of the variable resistanceelement is connected to the word line and a lower electrode of thevariable resistance element is connected to the bit line. In addition,it may be such that the lower electrode of the variable resistanceelement is connected to the word line and the upper electrode of thevariable resistance element is connected to the bit line so that therelation between the upper electrode and the lower electrode of thevariable resistance element is reversed.

Each of the bit line decoder 2 and the word line decoder 3 selects amemory cell to be read from the memory cell array 1 according to anaddress inputted from an address line 4 to the control circuit 6d. Theword line decoder 3 selects the word line in the memory cell array 1according to the signal inputted to the address line 4, and the bit linedecoder 2 selects the bit line in the memory cell array 1 according tothe address signal inputted to the address line 4. According to thisembodiment, in the programming action and the erasing action, the bitline decoder 2 and the word line decoder 3 function as memory cellselect circuits that select the memory cell from the memory cell array 1by the memory cell, and in the reading action, the word line decoder 3functions as a memory cell select circuit that selects the memory cellfrom the memory cell array 1 by the row.

The control circuit 6d controls each memory action of programming,erasing and reading of the memory cell array 1. The control circuit 6dcontrols the word line decoder 3, the bit line decoder 2, the voltageswitch circuit 8d and the reading, programming and erasing actions ofthe memory cell array 1, based on the address signal inputted from theaddress line 4, a data input (at the time of programming) inputted froma data line 5, and a control input signal inputted from a control signalline 7. According to the example shown in FIG. 8, the control circuit 6dis provided with a function as a general address buffer circuit, datainput/output buffer circuit, and control input buffer circuit thoughthey are not shown.

The voltage switch circuit 8d switches each voltage of the word line andbit line required for the reading action, programming action and erasingaction of the memory cell array 1 according to an action mode andsupplies it to the memory cell array 1. According to this embodiment, inthe reading action, the memory cells connected to one selected word lineselected by the word line decoder 3 become the selected memory cells,and in the programming action and the erasing action, the memory cellconnected to one selected word line selected by the word line decoder 3and to one or more selected bit lines selected by the bit line decoder 2becomes the selected memory cell, and according to each action mode ofthe programming, erasing and reading, a predetermined programmingvoltage V_(WE), erasing voltage V_(WE) or reading voltage V_(R) isapplied between the selected word line and the selected bit line. In thedrawing, reference character Vcc designates a power supply voltage ofthe device of the present invention, reference character Vss designatesthe ground voltage, reference character V_(WE) designates the programvoltage and erasing voltage, reference character V_(WE)/2 designates theunselect voltage having a half voltage value of the programming voltageV_(WE), reference character V1 _(R) designates a first reading voltage,which are supplied from the outside or generated in an internal circuit(not shown) and applied to the voltage switch circuit 8d and topredetermined word line and bit line. The first reading voltage V1 _(R)is used in generating the reading voltage V_(R) required for datareading of the 1R type memory cell.

In addition, the programming voltage V_(WE) is the voltage required fordata programming of the 1R type memory cell, and the erasing voltageV_(WE) is the voltage required for data erasing of the 1R type memorycell, which are the same voltage value in this embodiment and the samegoes for the following description of the present invention.

The reading circuit 9 converts a reading current flowing in the bit lineselected by the bit line decoder 2 among reading currents flowing in thebit line connected to the selected memory cell to a voltage, determinesthe state of memory data in the memory cell as a reading objectconnected to the selected bit line in the selected memory cells in onerow, transfers its result to the control circuit 6d and outputs it tothe data line 5.

Next, an electric pulse applying process for applying a predeterminedvoltage to each of the selected word line, selected bit line, unselectedword lines and unselected bit lines in each of the programming action,the erasing action and reading action of the data in the memory cellarray 1 according to this embodiment will be described with respect toeach memory action.

FIGS. 9 and 10 show one example of the electric pulse applying processin the programming action. When data is programmed in the selectedmemory cell, the voltage of all the word lines and all the bit lines ispreviously set to the half of the programming voltage V_(WE), that is,the unselect voltage V_(WE)/2 in a precharging time (action preparingtime) just before the programming action is started. Alternatively, thevoltage of all the word lines and all the bit lines may be set to theunselect voltage V_(WE)/2 in a standby time (that is neither theprogramming action, the erasing action nor reading action and a standbystate under low power consumption).

During a programming action period Tw, the unselect voltage V_(WE)/2that is the half of the programming voltage V_(WE) is continuouslyapplied to all the unselected word lines and all the unselected bitlines similar to during the precharge period, and the ground voltage Vss(corresponding to a second programming voltage) to the selected wordline and the programming voltage V_(WE) (corresponding to a firstprogramming voltage) is applied to the selected bit line. During theprogramming action period Tw, since a voltage deference of theprogramming voltage V_(WE) is generated between the selected bit lineand the selected word line, the programming voltage V_(WE) is applied tothe variable resistance element in the selected memory cell and data canbe programmed. At this time, although the unselect voltage V_(WE)/2 thatis the half of the programming voltage V_(WE) is applied to the memorycell connected to the selected word line and the unselected bit linesand the memory cell connected to the selected bit line and theunselected word lines, since the voltage is sufficiently lower than theprogramming voltage V_(WE), programming is not performed.

FIGS. 11 and 12 show one example of the electric pulse applying processat the time of the erasing action. When the data of the selected memorycell is erased, the voltage of all the word lines and all the bit linesis previously set to the half of the erasing voltage V_(WE), that is,the unselect voltage V_(WE)/2 in a precharging period (action preparingperiod) just before the erasing action is started. Alternatively, thevoltage of all the word lines and all the bit lines may be set to theunselect voltage V_(WE)/2 in a standby time of the device of the presentinvention.

During an erasing action period Te, the half unselect voltage V_(WE)/2of the erasing voltage V_(WE) is continuously applied to all theunselected word lines and all the unselected bit lines similar to duringthe precharging period, and the erasing voltage V_(WE) (corresponding toa first erasing voltage) is applied to the selected word line and theground voltage Vss (corresponding to a second erasing voltage) isapplied to the selected bit line. During the erasing action period Te,since a voltage deference of the erasing voltage V_(WE) that is the sameas the programming voltage V_(WE) but has the opposite polarity isgenerated between the selected word line and the selected bit line, theerasing voltage V_(WE) is applied to the variable resistance element inthe selected memory cell and data can be erased. At this time, althoughthe unselect voltage V_(WE)/2 that is the half of the erasing voltageV_(WE) is applied to the memory cell connected to the selected word lineand unselected bit lines and the memory cell connected to the selectedbit line and unselected word lines, since the voltage is sufficientlylower than the erasing voltage V_(WE), erasing is not performed.

FIGS. 13 and 14 show one example of the electric pulse applying processat the time of the reading action. When the data of the selected memorycell is read, the voltage of all the word lines and all the bit lines ispreviously set to the half of the programming voltage V_(WE), that is,unselect voltage V_(WE)/2 in a precharging period (action preparingperiod) just before the reading action is started. Alternatively, thevoltage of all the word lines and all the bit lines may be set to theunselect voltage V_(WE)/2 in a standby time of the device of the presentinvention.

During a reading action period Tr, the half unselect voltage V_(WE)/2 ofthe programming voltage V_(WE) is continuously applied to all theunselected word lines and all the unselected bit lines and the selectedbit line, and the first reading voltage V1 _(R) is applied to theselected word line. Here, the first reading voltage V1 _(R) is set tothe voltage difference (V1 _(R)−V_(WE)/2−V_(R)) between the unselectvoltage V_(WE)/2 and the reading voltage V_(R). As a result, since thevoltage deference of the reading voltage V_(R) is generated between theselected bit line and the selected word line during the reading actionperiod Tr, the reading voltage V_(R) can be applied to the variableresistance element of the selected memory cell, so that the state of theresistance of the variable resistance element can be read. The readingvoltage V_(R) is below the programming voltage V_(WE) and it only has tobe enough for the reading circuit 9 to read the data. The readingvoltage V_(R) can be the unselect voltage V_(WE)/2 that is the half ofthe programming voltage V_(WE) by adjusting the material, composition,film thickness, area and the like of the variable resistance element. Inthis case, since the first reading voltage V1 _(R) is equal to theground voltage Vss, the number of kinds of the voltages supplied to thevoltage switch circuit 8d can be reduced.

As described above, since the common unselect voltage V_(WE)/2 isapplied to the unselected word lines and the unselected bit lines duringeach memory action of programming, erasing, and reading and during theprecharging period of each action, in the case of moving to thedifferent memory action during a certain memory action or a case ofmoving to a certain memory action from a certain precharging period,each memory action can be performed only by changing the voltages of theselected word line and the selected bit line. Thus, the currentconsumption generated by a transient current accompanied by charging anddischarging of parasitic capacity, to set each word line and each bitline at a predetermined voltage during each memory action can beconsiderably reduced.

Second Embodiment

Next, a description will be made of a second embodiment in which theground voltage Vss is applied as the common unselect voltage, tounselected word lines and unselected bit lines in each memory action ofprogramming, erasing and reading in the device of the present invention,with reference to FIGS. 15 to 21.

FIG. 15 is a block diagram showing the functional constitution of adevice of the present invention according to the second embodiment. InFIG. 15, a description will be made such that a common sign is allottedto a part common to that in the conventional nonvolatile semiconductormemory device and the first embodiment. As shown in FIG. 15, the deviceof the present invention comprises a bit line decoder 2, a word linedecoder 3, a voltage switch circuit 8e, a reading circuit 9, and acontrol circuit 6e around a memory cell array 1 in which 1R type memorycells are arranged like a matrix as shown in FIG. 16. Basically, theconstitution is the same as that of the conventional nonvolatilesemiconductor memory device shown in FIG. 1 and the first embodiment inFIG. 8. It is different from the first embodiment in the voltagesapplied to each word line and each bit line of the memory cell array 1from the voltage switch circuit 8e and the control action of the appliedvoltage by the control circuit 6e. The constitution of the memory cellarray 1 is also the same as the memory cell arrays 1 of the conventionalnonvolatile semiconductor memory device shown in FIG. 2 and of the firstembodiment shown in FIG. 9.

The description will not be made of the same component in the firstembodiment but will be made of the voltage switch circuit 8e and thecontrol circuit 6e.

The control circuit 6e controls each memory action of programming,erasing and reading of the memory cell array 1 similar to the firstembodiment. Although the basic control action is the same as that of thefirst embodiment, it is different from the first embodiment in thatamong the voltages supplied from the voltage switch circuit 8e, theground voltage Vss is applied to the unselected word lines and theunselected bit lines as the unselect voltage. The control circuit 6econtrols the word line decoder 3, the bit line decoder 2, the voltageswitch circuit 8e and the reading, programming and erasing actions ofthe memory cell array 1, based on an address signal inputted from anaddress line 4, a data input (at the time of programming) inputted froma data line 5, and a control input signal inputted from a control signalline 7. In the example shown in FIG. 15, the control circuit 6e isprovided with a function as a general address buffer circuit, datainput/output buffer circuit, control input buffer circuit though theyare not shown.

The voltage switch circuit 8e switches each voltage of the word line andbit line required for the reading action, programming action and erasingaction of the memory cell array 1 according to an action mode andsupplies it to the memory cell array 1. Similar to the first embodiment,in the reading action, the memory cells connected to one selected wordline selected by the word line decoder 3 become the selected memorycells, and in the programming action and the erasing action, the memorycell connected to one selected word line selected by the word linedecoder 3 and to one or more selected bit lines selected by the bit linedecoder 2 becomes the selected memory cell, and according to each actionmode of the programming, erasing and reading, a predeterminedprogramming voltage V_(WE), erasing voltage V_(WE) or reading voltageV_(R) is applied between the selected word line and the selected bitline. In the drawing, reference character Vcc designates a power supplyvoltage of the device of the present invention, reference character Vssdesignates the ground voltage and the unselect voltage, referencecharacter V_(WE)/2 designates a first programming voltage and a firsterasing voltage, reference character −V_(WE)/2 designates a secondprogramming voltage and a second erasing voltage, and referencecharacter −V_(R) designates a first reading voltage, which are suppliedfrom the outside or generated in an internal circuit (not shown) andapplied to the voltage switch circuit 8e and to a certain word line andbit line.

Next, an electric pulse applying process for applying a predeterminedvoltage to each of the selected word line, selected bit line, unselectedword lines and unselected bit lines in each of the programming action,the erasing action and reading action of the data in the memory cellarray 1 according to the second embodiment will be described withrespect to each memory action.

FIGS. 16 and 17 show one example of the electric pulse applying processin the programming action. When data is programmed in the selectedmemory cell, the voltage of all the word lines and all the bit lines ispreviously set to the unselect voltage, that is, the ground voltage Vssin a precharging period (action preparing time) just before theprogramming action is started. Alternatively, the voltage of all theword lines and all the bit lines may be set to the unselect voltage Vssin a standby time of the device of the present invention.

During a programming action period Tw, the unselect voltage Vss iscontinuously applied to all unselected word lines and all unselected bitlines similar to during the precharging period, and the firstprogramming voltage V_(WE)/2 that is the half of the programming voltageV_(WE) is applied to the selected bit line and the second programmingvoltage −V_(WE)/2 that is the half of the programming voltage V_(WE) andhas negative polarity is applied to the selected word line. During theprogramming action period Tw, since a voltage deference of theprogramming voltage V_(WE) is generated between the selected bit lineand the selected word line, the programming voltage V_(WE) is applied tothe variable resistance element in the selected memory cell and data canbe programmed. At this time, although the first programming voltageV_(WE)/2 is applied to the memory cell connected to the selected wordline and unselected bit lines and the memory cell connected to theselected bit line and unselected word lines, since the voltage issufficiently lower than the programming voltage V_(WE), programming isnot performed.

FIGS. 18 and 19 show one example of the electric pulse applying processat the time of the erasing action. When the data of the selected memorycell is erased, the voltage of all the word lines and all the bit linesis previously set to the ground voltage Vss that is the unselect voltagein a precharging period (action preparing period) just before theerasing action is started. Alternatively, the voltage of all the wordlines and all the bit lines may be set to the unselect voltage Vss in astandby time of the device of the present invention.

During an erasing action period Te, the unselect voltage Vss iscontinuously applied to all unselected word lines and all unselected bitlines similar to during the precharging period, and the first erasingvoltage V_(WE)/2 that is the half of the erasing voltage V_(WE) isapplied to the selected word line and the second erasing voltage−V_(WE)/2 that is the half of the erasing voltage V_(WE) and has anegative polarity is applied to the selected bit line. During theerasing action period Te, since the voltage deference of the erasingvoltage V_(WE) that is equal to the programming voltage V_(WE) but hasthe opposite polarity is generated between the selected word line andthe selected bit line, the erasing voltage V_(WE) is applied to thevariable resistance element in the selected memory cell and data can beerased. At this time, although the first erasing voltage V_(WE)/2 isapplied to the memory cell connected to the selected word line andunselected bit lines and the memory cell connected to the selected bitline and unselected word lines, since the voltage is sufficiently lowerthan the erasing voltage V_(WE), erasing is not performed.

FIGS. 20 and 21 show one example of the electric pulse applying processat the time of the reading action. When the data of the selected memorycell is read, the voltage of all the word lines and all the bit lines ispreviously set to the unselect voltage that is the ground voltage Vss ina precharging period (action preparing period) just before the readingaction is started. Alternatively, the voltage of all the word lines andall the bit lines may be set to the unselect voltage Vss in a standbytime of the device of the present invention.

During a reading action period Tr, the unselect voltage Vss is appliedto all the unselected word lines and all the unselected bit lines andthe selected bit line, and the first reading voltage −V_(R) is appliedto the selected word line. Here, the first reading voltage −V_(R) is setto the voltage difference (−V_(R)−Vss−V_(R)) between the unselectvoltage Vss and the reading voltage V_(R), that is, set to the voltagethat is equal to the reading voltage V_(R) but opposite in polarity. Asa result, since the voltage deference of the reading voltage V_(R) isgenerated between the selected bit line and the selected word lineduring the reading action period Tr, the reading voltage V_(R) can beapplied to the variable resistance element of the selected memory cell,and the state of the resistance of the variable resistance element canbe read. The reading voltage V_(R) is below the programming voltageV_(WE) and it only has to be enough for the reading circuit 9 to readthe data. The reading voltage V_(R) can be the first programming voltageV_(WE)/2 that is the half of the programming voltage V_(WE) by adjustingthe material, composition, film thickness, area and the like of thevariable resistance element. In this case, since the first readingvoltage −V_(R) is equal to the second programming voltage −V_(WE)/2, thenumber of kinds of the voltages supplied to the voltage switch 8e can bereduced.

As described above, since the common unselect voltage Vss is applied tothe unselected word lines and the unselected bit lines during eachmemory action of programming, erasing, and reading and during theprecharging period, in the case of moving to the different memory actionduring a certain memory action or a case of moving to a certain memoryaction from a certain precharging period, each memory action can beperformed only by changing the voltages of the selected word line andthe selected bit line. Thus, the current consumption generated by thetransient current accompanied by charging and discharging of theparasitic capacity, to set each word line and each bit line at apredetermined voltage during each memory action can be considerablyreduced. In addition, since the absolute value of the maximum voltageapplied to the word line and the bit line in each action mode isV_(WE)/2, that is the half of the programming voltage V_(WE) and theerasing voltage V_(WE), or the reading voltage V_(R), the voltage usedin the device of the present invention is reduced, so that the currentconsumption is further reduced.

Third Embodiment

Next, a description will be made of a third embodiment in which a commonfirst unselect voltage V_(WE)/3 that is one third of the programmingvoltage V_(WE) is applied to the unselected word lines and theunselected bit lines in each memory action of programming, erasing andreading in the device of the present invention, with reference to FIGS.22 to 28.

FIG. 22 is a block diagram showing the functional constitution of thedevice of the present invention according to the third embodiment. InFIG. 22, a description will be made such that a common sign is allottedto a part common to that in the conventional nonvolatile semiconductormemory device and the first embodiment. As shown in FIG. 22, the deviceof the present invention comprises a bit line decoder 2, a word linedecoder 3, a voltage switch circuit 8f, a reading circuit 9, and acontrol circuit 6f around a memory cell array 1 in which 1R type memorycells are arranged like a matrix as shown in FIG. 23. Basically, theconstitution is the same as that of the conventional nonvolatilesemiconductor memory device shown in FIG. 1 and the first embodiment inFIG. 8. It is different from the first embodiment in the voltagesapplied to each word line and each bit line of the memory cell array 1from the voltage switch circuit 8f and the control action of the appliedvoltage by the control circuit 6f. The constitution of the memory cellarray 1 is also the same as the memory cell arrays 1 of the conventionalnonvolatile semiconductor memory device shown in FIG. 2 and of the firstembodiment shown in FIG. 9.

The description will not be made of the same component as that in thefirst embodiment but will be made of the voltage switch circuit 8f andthe control circuit 6f.

The control circuit 6f controls each memory action of programming,erasing and reading of the memory cell array 1 similar to the firstembodiment. Although the basic control action is the same as that of thefirst embodiment, it is different from the first embodiment in thatamong the voltages supplied from the voltage switch circuit 8f, thevoltage V_(WE)/3 that is one third of the programming voltage V_(WE) asa first unselect voltage and the voltage 2 V_(WE)/3 that is two thirdsof the programming voltage V,_(WE) as a second unselect voltage areapplied to the unselected word lines and the unselected bit lines. Thecontrol circuit 6f controls the word line decoder 3, the bit linedecoder 2, the voltage switch circuit 8f and the reading, programmingand erasing actions of the memory cell array 1, based on an addresssignal inputted from an address line 4, a data input (at the time ofprogramming) inputted from a data line 5, and a control input signalinputted from a control signal line 7. In the example shown in FIG. 22,the control circuit 6f is provided with a function as a general addressbuffer circuit, data input/output buffer circuit, and control inputbuffer circuit though they are not shown.

The voltage switch circuit 8f switches each voltage of the word line andthe bit line required for the reading action, programming action anderasing action of the memory cell array 1 according to an action modeand supplies it to the memory cell array 1. Similar to the firstembodiment, in the reading action, the memory cells connected to oneselected word line selected by the word line decoder 3 become theselected memory cells, and in the programming action and the erasingaction, the memory cell connected to one selected word line selected bythe word line decoder 3 and to one or more selected bit lines selectedby the bit line decoder 2 becomes the selected memory cell, andaccording to each action mode of the programming, erasing and reading, apredetermined programming voltage V_(WE), erasing voltage V_(WE) orreading voltage V_(R) is applied between the selected word line and theselected bit line. In the drawing, reference character Vcc designates apower supply voltage of the device of the present invention, referencecharacter Vss designates the ground voltage, reference character V_(WE)designates a programming voltage and an erasing voltage, referencecharacter V_(WE)/3 designates a first unselect voltage, referencecharacter 2 V_(WE)/3 designates a second unselect voltage, and referencecharacter V2 _(R) designates a first reading voltage, which are suppliedfrom the outside or generated in an internal circuit (not shown) andapplied to the voltage switch circuit 8f and to a certain word line andbit line. The first reading voltage V2 _(R) is used in generating thereading voltage V_(R) required for reading the data of the 1R typememory cell.

Next, an electric pulse applying process for applying a predeterminedvoltage to each of the selected word line, selected bit line, unselectedword lines and unselected bit lines in each of the programming action,the erasing action and reading action of the data in the memory cellarray 1 according to the third embodiment will be described with respectto each memory action.

FIGS. 23 and 24 show one example of the electric pulse applying processin the programming action. When data is programmed in the selectedmemory cell, the voltage of all the word lines and all the bit lines ispreviously set to the first unselect voltage V_(WE)/3 that is one thirdof the programming voltage V_(WE) in a precharging period (actionpreparing time) just before the programming action is started.Alternatively, the voltage of all the word lines and all the bit linesmay be set to the first unselect voltage V_(WE)/3 in a standby time ofthe device of the present invention.

During a programming action period Tw, the second unselect voltage2V_(WE)/3 that is two thirds of the programming voltage V_(WE) isapplied to all unselected word lines, the first unselect voltageV_(WE)/3 that is one third of the programming voltage V_(WE) is appliedto all unselected bit lines similar to during the precharging period,and the ground voltage Vss (corresponding to a second programmingvoltage) is applied to the selected word line, and the programmingvoltage V_(WE) (corresponding to a first programming voltage) is appliedto the selected bit line. During the programming action period Tw, sincethe voltage deference of the programming voltage V_(WE) is generatedbetween the selected bit line and the selected word line, theprogramming voltage V_(WE) is applied to the variable resistance elementin the selected memory cell and data can be programmed. At this time,although the first unselect voltage V_(WE)/3 that is one third of theprogramming voltage V_(WE) is applied to the memory cell connected tothe selected word line and unselected bit lines and the memory cellconnected to the selected bit line and unselected word lines, since thevoltage is sufficiently lower than the programming voltage V_(WE),programming is not performed.

FIGS. 25 and 26 show one example of the electric pulse applying processat the time of the erasing action. When the data of the selected memorycell is erased, the voltage of all the word lines and all the bit linesis previously set to the first unselect voltage V_(WE)/3 that is onethird of the erasing voltage V_(WE) in a precharging period (actionpreparing period) just before the erasing action is started.Alternatively, the voltage of all the word lines and all the bit linesmay be set to the first unselect voltage V_(WE)/3 in a standby time ofthe device of the present invention.

During an erasing action period Te, the first unselect voltage V_(WE)/3that is one third of the erasing voltage V_(WE) is continuously appliedto all unselected word lines similar to during the precharging period,the second unselect voltage 2V_(WE)/3 that is two thirds of the erasingvoltage V_(WE) is applied to all unselected bit lines, the erasingvoltage V_(WE) is applied to the selected word line, and the groundvoltage Vss is applied to the selected bit line. During the erasingaction period Te, since the voltage deference of the erasing voltageV_(WE) that is equal to the programming voltage V_(WE) but has theopposite polarity is generated between the selected word line and theselected bit line, the erasing voltage V_(WE) is applied to the variableresistance element in the selected memory cell and data can be erased.At this time, although the first unselect voltage V_(WE)/3 that is onethird of the erasing voltage V_(WE) is applied to the memory cellconnected to the selected word line and unselected bit lines and thememory cell connected to the selected bit line and unselected wordlines, since the voltage is sufficiently lower than the erasing voltageV_(WE), erasing is not performed.

FIGS. 27 and 28 show one example of the electric pulse applying processat the time of the reading action. When the data of the selected memorycell is read, the voltage of all the word lines and all the bit lines ispreviously set to the first unselect voltage V_(WE)/3 that is one thirdof the programming voltage V_(WE) in a precharging period (actionpreparing period) just before the reading action is started.Alternatively, the voltage of all the word lines and all the bit linesmay be set to the first unselect voltage V_(WE)/3 in a standby time ofthe device of the present invention.

During a reading action period Tr, the first unselect voltage V_(WE)/3is continuously applied to all unselected word lines and all unselectedbit lines and all selected bit line, and the first reading voltage V2_(R) is applied to the selected word line. Here, the first readingvoltage V2 _(R) is set to the voltage difference (V2_(R)−V_(WE)/3−V_(R)) between the first unselect voltage V_(WE)/3 and thereading voltage V_(R). As a result, since the voltage deference of thereading voltage V_(R) is generated between the selected bit line and theselected word line during the reading action period Tr, the readingvoltage V_(R) can be applied to the variable resistance element of theselected memory cell, and the state of the resistance of the variableresistance element can be read. The reading voltage V_(R) is below theprogramming voltage V_(WE) and it only has to be enough for readingcircuit 9 to read the data. The reading voltage V_(R) can be the firstunselect voltage V_(WE)/3 that is one third of the programming voltageV_(WE) by adjusting the material, composition, film thickness, area andthe like of the variable resistance element. In this case, since thefirst reading voltage V2 _(R) is equal to the ground voltage Vss, thenumber of kinds of the voltages supplied to the voltage switch 8f can bereduced.

As described above, since the common first unselect voltage V_(WE)/3 isapplied to the unselected word lines and the unselected bit lines duringthe precharging period of each memory action of programming, erasing,and reading, in the case of moving to a certain memory action from acertain precharging period, each memory action can be performed only bychanging the voltages of the selected word line and the selected bitline. In addition, between the reading action and programming action, byapplying the common first unselect voltage V_(WE)/3 to the unselectedbit lines in each action period, even when the action is directlyshifted between the reading action and programming action, the voltageis not changed in the unselected bit lines and the voltage change of theunselected word lines remains at the first unselect voltage V_(WE)/3.Furthermore, between the reading action and erasing action, by applyingthe common first unselect voltage V_(WE)/3 to the unselected word linesin each action period, even when the action is directly shifted betweenthe reading action and erasing action; the voltage is not changed in theunselected word lines and the voltage change of the unselected bit linesremains at the first unselect voltage V_(WE)/3. Thus, the currentconsumption generated by a transient current accompanied by charging anddischarging of the parasitic capacity, to set each word line and eachbit line at a predetermined voltage during each memory action can beconsiderably reduced.

Fourth Embodiment

Next, a description will be made of a fourth embodiment in which thecommon second unselect voltage 2V_(WE)/3 that is two thirds of theprogramming voltage V_(WE) is applied to the unselected word lines andthe unselected bit lines in each memory action of programming, erasingand reading in the device of the present invention, with reference toFIGS. 29 to 35.

FIG. 29 is a block diagram showing the functional constitution of adevice of the present invention according to the third embodiment. InFIG. 29, a description will be made such that a common sign is allottedto a part common to that in the conventional nonvolatile semiconductormemory device and the first embodiment. As shown in FIG. 29, the deviceof the present invention comprises a bit line decoder 2, a word linedecoder 3, a voltage switch circuit 8g, a reading circuit 9, and acontrol circuit 6g around a memory cell array 1 in which 1R type memorycells are arranged like a matrix as shown in FIG. 30. Basically, theconstitution is the same as that of the conventional nonvolatilesemiconductor memory device shown in FIG. 1 and the first embodiment inFIG. 8. It is different from the first embodiment in the voltagesapplied to each word line and each bit line of the memory cell array 1from the voltage switch circuit 8g and the control action of the appliedvoltage by the control circuit 6g. The constitution of the memory cellarray 1 is also the same as the memory cell array 1 of the conventionalnonvolatile semiconductor memory device shown in FIG. 2 and the firstembodiment shown in FIG. 9.

The description will not be made of the same component as that in thefirst embodiment but will be made of the voltage switch circuit 8g andthe control circuit 6g.

The control circuit 6g controls each memory action of programming,erasing and reading of the memory cell array 1 similar to the firstembodiment. Although the basic control action is the same as that of thefirst embodiment, it is different from the first embodiment in thatamong the voltages supplied from the voltage switch circuit 8g, thevoltage V_(WE)/3 that is one third of the programming voltage V_(WE) asa first unselect voltage and the voltage 2V_(WE)/3 that is two thirds ofthe programming voltage V_(WE) as a second unselect voltage are appliedto the unselected word lines and the unselected bit lines. The controlcircuit 6g controls the word line decoder 3, the bit line decoder 2, thevoltage switch circuit 8g and the reading, programming and erasingactions of the memory cell array 1, based on an address signal inputtedfrom an address line 4, a data input (at the time of programming)inputted from a data line 5, and a control input signal inputted from acontrol signal line 7. In the example shown in FIG. 29, the controlcircuit 6g is provided with a function as a general address buffercircuit, data input/output buffer circuit, control input buffer circuitthough they are not shown.

The voltage switch circuit 8g switches each voltage of the word line andbit line required for the reading action, programming action and erasingaction of the memory cell array 1 according to an action mode andsupplies it to the memory cell array 1. Similar to the first embodiment,in the reading action, the memory cells connected to one selected wordline selected by the word line decoder 3 become the selected memorycells, and in the programming action and the erasing action, the memorycell connected to one selected word line selected by the word linedecoder 3 and to one or more selected bit lines selected by the bit linedecoder 2 becomes the selected memory cell, and according to each actionmode of the programming, erasing and reading, the predeterminedprogramming voltage V_(WE), erasing voltage V_(WE) or reading voltageV_(R) is applied between the selected word line and the selected bitline. In the drawing, reference character Vcc designates a power supplyvoltage of the device of the present invention, reference character Vssdesignates the ground voltage, reference character V_(WE) designates aprogramming voltage and an erasing voltage, reference character V_(WE)/3designates a first unselect voltage, reference character 2 V_(WE)/3designates a second unselect voltage, and reference character V3 _(R)designates a first reading voltage, which are supplied from the outsideor generated in an internal circuit (not shown) and applied to thevoltage switch circuit 8g and to a certain word line and bit line. Thefirst reading voltage V3 _(R) is used in generating the reading voltageV_(R) required for reading the data of the 1R type memory cell.

Next, an electric pulse applying process for applying a predeterminedvoltage to each of the selected word line, selected bit line, unselectedword lines and unselected bit lines in each of the programming action,the erasing action and reading action of the data in the memory cellarray 1 according to the fourth embodiment will be described withrespect to each memory action.

FIGS. 30 and 31 show one example of the electric pulse applying processin the programming action. When data is programmed in the selectedmemory cell, the voltage of all the word lines and all the bit lines ispreviously set to the second unselect voltage 2V_(WE)/3 that is twothirds of the programming voltage V_(WE) in a precharging period (actionpreparing time) just before the programming action is started.Alternatively, the voltage of all the word lines and all the bit linesmay be set to the second unselect voltage 2V_(WE)/3 in a standby time.

During a programming action period Tw, the second unselect voltage2V_(WE)/3 that is two thirds of the programming voltage V_(WE) iscontinuously applied to all unselected word lines similar to during theprecharging period, the first unselect voltage V_(WE)/3 that is onethird of the programming voltage V_(WE) is applied to all unselected bitlines, and the ground voltage Vss (corresponding to the secondprogramming voltage) is applied to the selected word line, and theprogramming voltage V_(WE) (corresponding to the first programmingvoltage) is applied to the selected bit line. During the programmingaction period Tw, since the voltage deference of the programming voltageV_(WE) is generated between the selected bit line and the selected wordline, the programming voltage V_(WE) is applied to the variableresistance element in the selected memory cell and data can beprogrammed. At this time, although the first unselect voltage V_(WE)/3that is one third of the programming voltage V_(WE) is applied to thememory cell connected to the selected word line and unselected bit linesand the memory cell connected to the selected bit line and unselectedword lines, since the voltage is sufficiently lower than the programmingvoltage V_(WE), programming is not performed.

FIGS. 32 and 33 show one example of the electric pulse applying processat the time of the erasing action. When the data of the selected memorycell is erased, the voltage of all the word lines and all the bit linesis previously set to the second unselect voltage 2V_(WE)/3 that is twothirds of the erasing voltage V_(WE) in a precharging period (actionpreparing period) just before the erasing action is started.Alternatively, the voltage of all the word lines and all the bit linesmay be set to the second unselect voltage 2V_(WE)/3 in a standby time ofthe device of the present invention.

During an erasing action period Te, the second unselect voltage2V_(WE)/3 that is two thirds of the erasing voltage V_(WE) iscontinuously applied to all unselected bit lines similar to during theprecharging period, the first unselect voltage V_(WE)/3 that is onethird of the erasing voltage V_(WE) is applied to all unselected wordlines, the erasing voltage V_(WE) is applied to the selected word line,and the ground voltage Vss is applied to the selected bit line. Duringthe erasing action period Te, since the voltage deference of the erasingvoltage V_(WE) that is equal to the programming voltage V_(WE) but hasthe opposite polarity is generated between the selected word line andthe selected bit line, the erasing voltage V_(WE) is applied to thevariable resistance element in the selected memory cell and data can beerased. At this time, although the first unselect voltage V_(WE)/3 thatis one third of the erasing voltage V_(WE) is applied to the memory cellconnected to the selected word line and unselected bit lines and thememory cell connected to the selected bit line and unselected wordlines, since the voltage is sufficiently lower than the erasing voltageV_(WE), erasing is not performed.

FIGS. 34 and 35 show one example of the electric pulse applying processat the time of the reading action. When the data of the selected memorycell is read, the voltage of all the word lines and all the bit lines ispreviously set to the second unselect voltage 2V_(WE)/3 that is twothirds of the programming voltage V_(WE) in a precharging period (actionpreparing period) just before the reading action is started.Alternatively, the voltage of all the word lines and all the bit linesmay be set to the second unselect voltage 2V_(WE)/3 in a standby time ofthe device of the present invention.

During a reading action period Tr, the second unselect voltage 2V_(WE)/3is continuously applied to all unselected word lines and all unselectedbit lines and the selected bit line, and the first reading voltage V3_(R) is applied to the selected word line. Here, the first readingvoltage V3 _(R) is set to the voltage difference (V3_(R)−2V_(WE)/3V_(R)) between the second unselect voltage 2V_(WE)/3 andthe reading voltage V_(R). As a result, since the voltage deference ofthe reading voltage V_(R) is generated between the selected bit line andthe selected word line during the reading action period Tr, the readingvoltage V_(R) can be applied to the variable resistance element of theselected memory cell, and the state of the resistance of the variableresistance element can be read. The reading voltage V_(R) is below theprogramming voltage V_(WE) and it only has to be enough for readingcircuit 9 to read the data. The reading voltage V_(R) can be the firstunselect voltage V_(WE)/3 that is one third of the programming voltageV_(WE) by adjusting the material, composition, film thickness, area andthe like of the variable resistance element. In this case, since thefirst reading voltage V3 _(R) is equal to the first unselect voltageV_(WE)/3, the number of kinds of the voltages supplied to the voltageswitch 8g can be reduced.

As described above, since the common second unselect voltage 2V_(WE)/3is applied to the unselected word lines and the unselected bit linesduring the precharging period in each memory action of programming,erasing, and reading, in the case of moving to a certain memory actionfrom a certain precharging period, each memory action can be performedonly by changing the voltages of the selected word line and the selectedbit line. In addition, between the reading action and the programmingaction, by applying the common second unselect voltage 2V_(WE)/3 to theunselected word lines in each action period, even when the action isdirectly shifted between the reading action and programming action, thevoltage is not changed in the unselected word lines and the voltagechange of the unselected bit lines remains at the first unselect voltageV_(WE)/3. Furthermore, between the reading action and erasing action, byapplying the common second unselect voltage 2V_(WE)/3 to the unselectedbit lines in each action period, even when the action is directlyshifted between the reading action and erasing action, the voltage isnot changed in the unselected bit lines and the voltage change of theunselected word lines remains at the first unselect voltage V_(WE)/3.Thus, the current consumption generated by a transient currentaccompanied by charging and discharging of the parasitic capacity, toset each word line and each bit line at a predetermined voltage duringeach memory action can be considerably reduced.

Next, another embodiment of the device and method of the presentinvention will be described.

(1) Although the case where one word line is selected and the readingcurrent flowing in the selected memory cells connected to that selectedword line is selected on the bit line side and read has been describedin the above first to fourth embodiments, the relation between the wordline and the bit line may be reversed such that one bit line is selectedand the reading current flowing in the selected memory cells connectedto that selected bit line is selected on the word line side and read. Inthis case, the reading circuit 9 is connected to the word line decoder3.

(2) Although the voltage switch circuits 8d, 8e, 8f, or 8g shown in FIG.8, 15, 22 or 29 generates the voltages for programming, erasing andreading in the above first to fourth embodiments, there may be providedcircuits each generating the voltage for each action.

As described above, according to the device and method of the presentinvention, the current consumption of the non-volatile semiconductormemory device comprising the memory cell array in which the 1R typememory cells are arranged in the row and column directions like a matrixcan be reduced by reducing the number of the word lines and bit lines inwhich the potential is changed at the time of shifting between thememory actions to reduce the transient current caused by the chargingand discharging of the parasitic capacity in each word line and each bitline.

INDUSTRIAL APPLICABILITY

The present invention can be applied to a nonvolatile semiconductormemory device and particularly to a voltage control technique for thebit line and word line in each memory action of reading, programming anderasing in a semiconductor memory device comprising a memory cell arrayin which two-terminal memory cells comprising a variable resistanceelement having a resistance value reversibly changed by electric pulseapplication and storing information by the change of the electricresistance are arranged in the row direction and column direction.

The invention claimed is:
 1. A nonvolatile semiconductor memory devicecomprising: a memory cell array comprising including two-terminal memorycells each comprising a variable resistance element having a resistancevalue reversibly changed by electric pulse application, the memory cellsbeing arranged in a row direction and column direction such that one endof each memory cell in the same row is connected to a common word lineand the other end of each memory cell in the same column is connected toa common bit line; a memory cell selecting circuit selecting theconfigured to select a memory cell from the memory cell array by therow, column or or column of the memory cell array; a voltage switchcircuit applying configured to apply a voltage required for each of aplurality of memory actions including a reading action, a programmingaction and an erasing action in the memory cell selected by the memorycell selecting circuit, to a selected word line and a selected bit lineconnected to a the selected memory cell and to unselected word lines andunselected bit lines other than the above selected word line andselected bit line among word lines and bit lines, according to thememory actions; and a reading circuit reading configured to readinformation stored in the selected memory cell to be read in theselected memory cells by detecting the an amount of a reading currentflowing according to the resistance value of the variable resistanceelement in the selected memory cell to be read, wherein the voltageswitch circuit applies is further configured to: apply a common unselectvoltage to both the unselected word lines and the unselected bit linesduring each of the reading, actions; apply the common unselect voltageto both the unselected word lines and the unselected bit lines duringthe programming actions; and apply the common unselect voltage to boththe unselected word lines and the unselected bit lines during theerasing actions, wherein the common unselect voltage has an absolutevalue greater than zero.
 2. A nonvolatile semiconductor memory devicecomprising: a memory cell array comprising including two-terminal memorycells each comprising a variable resistance element having a resistancevalue reversibly changed by electric pulse application, the memory cellsbeing arranged in a row direction and column direction such that one endof each memory cell in the same row is connected to a common word lineand the other end of each memory cell in the same column is connected toa common bit line; a memory cell selecting circuit configured to selecta memory cell by selecting the memory cell from the memory cell array bythe row, column or column of the memory cell array; a voltage switchcircuit applying configured to apply a voltage required for each of aplurality of memory actions including a reading action, a programmingaction and an erasing action in the memory cell selected by the memorycell selecting circuit, to a selected word line and a selected bit lineconnected to a the selected memory cell and to unselected word lines andunselected bit lines other than the above selected word line andselected bit line among word lines and bit lines, according to thememory actions; and a reading circuit reading configured to readinformation stored in the selected memory cell to be read in theselected memory cells by detecting the an amount of a reading currentflowing according to the resistance value of the variable resistanceelement in the selected memory cell to be read, wherein the voltageswitch circuit applies is further configured to: apply a common unselectvoltage to one of the unselected word lines and the unselected bit linesat least during each of the reading actions and the programming actions,and applies to apply the common unselect voltage to the other of theunselected word lines and the unselected bit lines at least during eachof the reading actions and the erasing actions, or apply the commonunselect voltage to the unselected bit lines during the reading actionsand the programming actions and to apply the common unselect voltage tothe unselected word lines during the reading actions and the erasingactions, and wherein the common unselect voltage has an absolute valuegreater than zero.
 3. The nonvolatile semiconductor memory deviceaccording to claim 1, wherein the voltage switch circuit applies isfurther configured to apply the common unselect voltage to at least theunselected word lines and the unselected bit lines during each of actionpreparing periods just before the reading, programming and erasingactions.
 4. The nonvolatile semiconductor memory device according toclaim 3, wherein the common unselect voltage is applied to the selectedword line and the selected bit line during each of the action preparingperiods.
 5. The nonvolatile semiconductor memory device according toclaim 1, wherein the voltage switch circuit applies the common unselectvoltage to one of the selected word line and the selected bit line andboth of the unselected word lines and the unselected bit lines andapplies a first reading voltage different from the unselect voltage tothe other of the selected word line and the selected bit line, duringthe reading action, and wherein the absolute value of voltage differencebetween the first reading voltage and the unselect voltage is apredetermined reading voltage lower than the lower limit value ofabsolute values of a programming voltage required for the programmingaction for the variable resistance element and an erasing voltagerequired for the erasing action for the variable resistance element. 6.The nonvolatile semiconductor memory device according to claim 1,wherein the voltage switch circuit applies is further configured toapply a first programming voltage higher than the common unselectvoltage to one of the selected word line and the selected bit line andapplies a second programming voltage lower than the common unselectvoltage to the other of the selected word line and the selected bit lineduring the programming action, and wherein the absolute value of voltagedifference between the first programming voltage and the secondprogramming voltage is a programming voltage required for theprogramming action for the variable resistance element.
 7. Thenonvolatile semiconductor memory device according to claim 1, whereinthe voltage switch circuit applies is further configured to apply afirst erasing voltage higher than the common unselect voltage to one ofthe selected word line and selected bit line and applies a seconderasing voltage lower than the common unselect voltage to the other ofthe selected word line and the selected bit line during the erasingaction, and wherein the absolute value of voltage difference between thefirst erasing voltage and the second erasing voltage is an erasingvoltage required for the erasing action for the variable resistanceelement.
 8. The nonvolatile semiconductor memory device according toclaim 1, wherein the voltage switch circuit applies is furtherconfigured to apply a first programming voltage higher than the commonunselect voltage to one of the selected word line and selected bit lineand applies a second programming voltage lower than the common unselectvoltage to the other of the selected word line and the selected bit lineduring the programming action, and applies a first erasing voltagehigher than the common unselect voltage to the other of the selectedword line and selected bit line and applies a second erasing voltagelower than the common unselect voltage to one of the selected word lineand the selected bit line during the erasing action, wherein theabsolute value of voltage difference between the first programmingvoltage and the second programming voltage is a programming voltagerequired for the programming action for the variable resistance element,and the absolute value of voltage difference between the first erasingvoltage and the second erasing voltage is an erasing voltage requiredfor the erasing action for the variable resistance element, and whereinthe first programming voltage is equal to the first erasing voltage andthe second programming voltage is equal to the second erasing voltage.9. The nonvolatile semiconductor memory device according to claim 1,wherein a voltage applied to the selected word line or the selected bitline during both of the programming and erasing actions is the groundvoltage, and wherein the common unselect voltage is half of aprogramming voltage required for the programming action for the variableresistance element or an erasing voltage required for the erasing actionfor the variable resistance element.
 10. The nonvolatile semiconductormemory device according to claim 1, wherein a voltage applied to theselected word line or the selected bit line during both of theprogramming and erasing actions is the ground voltage, and the unselectvoltage is one third of a programming voltage required for theprogramming action for the variable resistance element or an erasingvoltage required for the erasing action for the variable resistanceelement.
 11. The nonvolatile semiconductor memory device according toclaim 1, wherein a voltage applied to the selected word line or theselected bit line during both of the programming and erasing actions isthe ground voltage, and the unselect voltage is two thirds of aprogramming voltage required for the programming action for the variableresistance element or an erasing voltage required for the erasing actionfor the variable resistance element.
 12. The nonvolatile semiconductormemory device according to claim 1, wherein a polarity of one ofvoltages applied to the selected word line and the selected bit line ispositive and a polarity of the other thereof is negative during both ofthe programming and erasing actions, and the absolute values of them isthe same, and the unselect voltage is the ground voltage.
 13. Thenonvolatile semiconductor memory device according to claim 1, whereinthe voltage switch circuit applies is further configured to apply thecommon unselect voltage to the selected word line, selected bit line,unselected word lines and unselected bit lines in a standby state inwhich none of the reading, programming and erasing actions is performed.14. The nonvolatile semiconductor memory device according to claim 1,wherein the material of the variable resistance element is comprises ametal oxide.
 15. The nonvolatile semiconductor memory device accordingto claim 1 14, wherein the metal oxide as the material of the variableresistance element is comprises a transition metal oxide.
 16. Thenonvolatile semiconductor memory device according to claim 1 14, whereinthe metal oxide as the material of the variable resistance elementcontains comprises Pr and Mn.
 17. An operating method in a nonvolatilesemiconductor memory device comprising a memory cell array comprisingincluding two-terminal memory cells each comprising a variableresistance element having a resistance value reversibly changed byelectric pulse application, the memory cells being arranged in a rowdirection and column direction such that one end of each memory cell inthe same row is connected to a common word line and the other end ofeach memory cell in the same column is connected to a common bit line,for a plurality of memory actions including a reading action, aprogramming action and an erasing action in a selected memory cellselected from the memory cell array by the row, or column, or memorycell of the memory cell array, the operating method comprising: applyinga common unselect voltage to both of unselected word lines andunselected bit lines that are not connected to the selected memory cellamong word lines and bit lines during each of the reading, programmingand erasing actions.; applying the common unselect voltage to both theunselected word lines and the unselected bit lines during theprogramming actions; and applying the common unselect voltage to boththe unselected word lines and the unselected bit lines during theerasing actions, wherein the common unselect voltage has an absolutevalue greater than zero.
 18. An operating method in a nonvolatilesemiconductor memory device comprising a memory cell array comprisingincluding two-terminal memory cells each comprising a variableresistance element having a resistance value reversibly changed byelectric pulse application, the memory cells being arranged in a rowdirection and column direction such that one end of each memory cell inthe same row is connected to a common word line and the other end ofeach memory cell in the same column is connected to a common bit line,for a plurality of memory actions including a reading action, aprogramming action and an erasing action in a selected memory cellselected from the memory cell array by the row, or column, or memorycell of the memory cell array, the operating method comprising: applyinga common unselect voltage to one of unselected word lines and unselectedbit lines that are not connected to the selected memory cell among wordlines and bit lines at least during each of the reading actions and theprogramming actions, and to apply the common unselect voltage to theother of the unselected word lines and the unselected bit lines at leastthat are not connected to the selected memory cell among bit linesduring each of the reading actions and the erasing actions, or applyingthe common unselect voltage to the unselected bit lines during thereading actions and the programming actions and to apply the commonunselect voltage to the unselected word lines during the reading actionsand the erasing actions, wherein the common unselect voltage has anabsolute value greater than zero.
 19. The operating method of thenonvolatile semiconductor memory device according to claim 17comprising: applying the common unselect voltage to the unselected wordlines and the unselected bit lines during each of action preparingperiods just before the reading, programming and erasing actions. 20.The operating method of the nonvolatile semiconductor memory deviceaccording to claim 19 comprising: applying the common unselect voltageto a selected word line and a selected bit line connected to theselected memory cell among the word lines and bit lines during each ofthe action preparing periods.
 21. The operating method of thenonvolatile semiconductor memory device according to claim 17comprising: applying the common unselect voltage to one of a selectedword line and a selected bit line connected to the selected memory celland both of the unselected word lines and the unselected bit lines and afirst reading voltage different from the unselect voltage to the otherof the selected word line and the selected bit line, among the wordlines and bit lines, during the reading action, wherein the absolutevalue of voltage difference between the first reading voltage and thecommon unselect voltage is a predetermined reading voltage lower thanthe lower limit value of absolute values of a programming voltagerequired for the programming action for the variable resistance elementand an erasing voltage required for the erasing action for the variableresistance element.
 22. The operating method of the nonvolatilesemiconductor memory device according to claim 17, wherein a voltageapplied to one of a selected word line and a selected bit line connectedto the selected memory cell among the word lines and the bit linesduring both of the programming and erasing actions is the groundvoltage, and wherein the common unselect voltage is half of aprogramming voltage required for the programming action for the variableresistance element or an erasing voltage required for the erasing actionfor the variable resistance element.
 23. The operating method of thenonvolatile semiconductor memory device according to claim 17, wherein avoltage applied to one of a selected word line and a selected bit lineconnected to the selected memory cell among the word lines and the bitlines during both of the programming and erasing actions is the groundvoltage, and the unselect voltage is one third of a programming voltagerequired for the programming action for the variable resistance elementor an erasing voltage required for the erasing action for the variableresistance element.
 24. The operating method of the nonvolatilesemiconductor memory device according to claim 17, wherein a voltageapplied to one of a selected word line and a selected bit line connectedto the selected memory cell among the word lines and the bit linesduring both of the programming and erasing actions is the groundvoltage, and the unselect voltage is two thirds of a programming voltagerequired for the programming action for the variable resistance elementor an erasing voltage required for the erasing action for the variableresistance element.
 25. The operating method of the nonvolatilesemiconductor memory device according to claim 17, wherein a polarity ofone of voltages applied to a selected word line and a selected bit lineconnected to the selected memory cell among the word lines and the bitlines during both of the programming and erasing actions is positive anda polarity of the other thereof is negative, and the absolute values ofthem is the same, and the unselect voltage is the ground voltage. 26.The operating method of the nonvolatile semiconductor memory deviceaccording to claim 17, wherein the voltage switch circuit applies thecommon unselect voltage to a selected word line and selected bit lineconnected to the selected memory cell, and the unselected word lines andunselected bit lines among the word lines and bit lines in a standbystate in which none of the reading, programming, and erasing actions isperformed.
 27. The operating method of the nonvolatile semiconductormemory device according to claim 17, wherein the material of thevariable resistance element is comprises a metal oxide.
 28. Theoperating method of the nonvolatile semiconductor memory deviceaccording to claim 17 27, wherein the metal oxide as the material of thevariable resistance element is comprises a transition metal oxide. 29.The operating method of the nonvolatile semiconductor memory deviceaccording to claim 17 27, wherein the metal oxide as the material of thevariable resistance element contains comprises Pr and Mn.
 30. Thenonvolatile semiconductor memory device according to claim 2, whereinthe voltage switch circuit applies is further configured to apply thecommon unselect voltage to at least the unselected word lines and theunselected bit lines during each of action preparing periods just beforethe reading, programming and erasing actions.
 31. The nonvolatilesemiconductor memory device according to claim 2, wherein the voltageswitch circuit applies is further configured to apply the commonunselect voltage to one of the selected word line and the selected bitline and both of the unselected word lines and the unselected bit linesand applies a first reading voltage different from the common unselectvoltage to the other of the selected word line and the selected bitline, during the reading action, and wherein the absolute value ofvoltage difference between the first reading voltage and the commonunselect voltage is a predetermined reading voltage lower than the lowerlimit value of absolute values of a programming voltage required for theprogramming action for the variable resistance element and an erasingvoltage required for the erasing action for the variable resistanceelement.
 32. The nonvolatile semiconductor memory device according toclaim 2, wherein the voltage switch circuit applies is furtherconfigured to apply a first programming voltage higher than the commonunselect voltage to one of the selected word line and the selected bitline and applies a second programming voltage lower than the commonunselect voltage to the other of the selected word line and the selectedbit line during the programming action, and wherein the absolute valueof voltage difference between the first programming voltage and thesecond programming voltage is a programming voltage required for theprogramming action for the variable resistance element.
 33. Thenonvolatile semiconductor memory device according to claim 2, whereinthe voltage switch circuit applies is further configured to apply afirst erasing voltage higher than the common unselect voltage to one ofthe selected word line and selected bit line and applies a seconderasing voltage lower than the common unselect voltage to the other ofthe selected word line and the selected bit line during the erasingaction, and wherein the absolute value of voltage difference between thefirst erasing voltage and the second erasing voltage is an erasingvoltage required for the erasing action for the variable resistanceelement.
 34. The nonvolatile semiconductor memory device according toclaim 2, wherein the voltage switch circuit applies is furtherconfigured to apply a first programming voltage higher than the commonunselect voltage to one of the selected word line and selected bit lineand applies a second programming voltage lower than the common unselectvoltage to the other of the selected word line and the selected bit lineduring the programming action, and applies a first erasing voltagehigher than the common unselect voltage to the other of the selectedword line and selected bit line and applies a second erasing voltagelower than the common unselect voltage to one of the selected word lineand the selected bit line during the erasing action, wherein theabsolute value of voltage difference between the first programmingvoltage and the second programming voltage is a programming voltagerequired for the programming action for the variable resistance element,and the absolute value of voltage difference between the first erasingvoltage and the second erasing voltage is an erasing voltage requiredfor the erasing action for the variable resistance element, and whereinthe first programming voltage is equal to the first erasing voltage andthe second programming voltage is equal to the second erasing voltage.35. The nonvolatile semiconductor memory device according to claim 2,wherein a voltage applied to the selected word line or the selected bitline during both of the programming and erasing actions is the groundvoltage, and wherein the common unselect voltage is half of aprogramming voltage required for the programming action for the variableresistance element or an erasing voltage required for the erasing actionfor the variable resistance element.
 36. The nonvolatile semiconductormemory device according to claim 2, wherein a voltage applied to theselected word line or the selected bit line during both of theprogramming and erasing actions is the ground voltage, and wherein thecommon unselect voltage is one third of a programming voltage requiredfor the programming action for the variable resistance element or anerasing voltage required for the erasing action for the variableresistance element.
 37. The nonvolatile semiconductor memory deviceaccording to claim 2, wherein a voltage applied to the selected wordline or the selected bit line during both of the programming and erasingactions is the ground voltage, and wherein the common unselect voltageis two thirds of a programming voltage required for the programmingaction for the variable resistance element or an erasing voltagerequired for the erasing action for the variable resistance element. 38.The nonvolatile semiconductor memory device according to claim 2,wherein a polarity of one of voltages applied to the selected word lineand the selected bit line is positive and a polarity of the otherthereof is negative during both of the programming and erasing actions,and the absolute values of them is the same, and the unselect voltage isthe ground voltage.
 39. The nonvolatile semiconductor memory deviceaccording to claim 2, wherein the voltage switch circuit applies isfurther configured to apply the common unselect voltage to the selectedword line, selected bit line, unselected word lines and unselected bitlines in a standby state in which none of the reading, programming anderasing actions is performed.
 40. The nonvolatile semiconductor memorydevice according to claim 2, wherein the material of the variableresistance element is comprises a metal oxide.
 41. The nonvolatilesemiconductor memory device according to claim 2 40, wherein the metaloxide as the material of the variable resistance element is comprises atransition metal oxide.
 42. The nonvolatile semiconductor memory deviceaccording to claim 2 40, wherein the metal oxide as the material of thevariable resistance element contains comprises Pr and Mn.
 43. Theoperating method of the nonvolatile semiconductor memory deviceaccording to claim 18 comprising: applying the common unselect voltageto the unselected word lines and the unselected bit lines during each ofaction preparing periods just before the reading, programming anderasing actions.
 44. The operating method of the nonvolatilesemiconductor memory device according to claim 18 comprising: applyingthe common unselect voltage to one of a selected word line and aselected bit line connected to the selected memory cell and both of theunselected word lines and the unselected bit lines and a first readingvoltage different from the common unselect voltage to the other of theselected word line and the selected bit line, among the word lines andbit lines, during the reading action, wherein the absolute value ofvoltage difference between the first reading voltage and the commonunselect voltage is a predetermined reading voltage lower than the lowerlimit value of absolute values of a programming voltage required for theprogramming action for the variable resistance element and an erasingvoltage required for the erasing action for the variable resistanceelement.
 45. The operating method of the nonvolatile semiconductormemory device according to claim 18, wherein a voltage applied to one ofa selected word line and a selected bit line connected to the selectedmemory cell among the word lines and the bit lines during both of theprogramming and erasing actions is the ground voltage, and wherein thecommon unselect voltage is half of a programming voltage required forthe programming action for the variable resistance element or an erasingvoltage required for the erasing action for the variable resistanceelement.
 46. The operating method of the nonvolatile semiconductormemory device according to claim 18, wherein a voltage applied to one ofa selected word line and a selected bit line connected to the selectedmemory cell among the word lines and the bit lines during both of theprogramming and erasing actions is the ground voltage, and wherein thecommon unselect voltage is one third of a programming voltage requiredfor the programming action for the variable resistance element or anerasing voltage required for the erasing action for the variableresistance element.
 47. The operating method of the nonvolatilesemiconductor memory device according to claim 18, wherein a voltageapplied to one of a selected word line and a selected bit line connectedto the selected memory cell among the word lines and the bit linesduring both of the programming and erasing actions is the groundvoltage, and wherein the common unselect voltage is two thirds of aprogramming voltage required for the programming action for the variableresistance element or an erasing voltage required for the erasing actionfor the variable resistance element.
 48. The operating method of thenonvolatile semiconductor memory device according to claim 18, wherein apolarity of one of voltages applied to a selected word line and aselected bit line connected to the selected memory cell among the wordlines and the bit lines during both of the programming and erasingactions is positive and a polarity of the other thereof is negative, andthe absolute values of them is the same, and the unselect voltage is theground voltage.
 49. The operating method of the nonvolatilesemiconductor memory device according to claim 18, wherein the voltageswitch circuit applies is further configured to apply the commonunselect voltage to a selected word line and selected bit line connectedto the selected memory cell, and the unselected word lines andunselected bit lines among the word lines and bit lines in a standbystate in which none of the reading, programming, and erasing actions isperformed.
 50. The operating method of the nonvolatile semiconductormemory device according to claim 18, wherein the material of thevariable resistance element is comprises a metal oxide.
 51. Theoperating method of the nonvolatile semiconductor memory deviceaccording to claim 18 50, wherein the metal oxide as the material of thevariable resistance element is comprises a transition metal oxide. 52.The operating method of the nonvolatile semiconductor memory deviceaccording to claim 18 50, wherein the metal oxide as the material of thevariable resistance element contains comprises Pr and Mn.
 53. A memorydevice comprising: a memory cell array including memory cells, wherein afirst terminal of each memory cell in a same row is connected to acommon word line, and wherein a second terminal of each memory cell in asame column is connected to a common bit line; and a voltage switchcircuit configured to apply a voltage for each of a plurality of memoryactions to a selected word line and a selected bit line connected to aselected memory cell and to unselected word lines and unselected bitlines according to the plurality of memory actions, wherein theplurality of memory actions include a reading action, a programmingaction, and an erasing action in the selected memory cell; wherein thevoltage switch circuit is further configured to: apply a common unselectvoltage to both the unselected word lines and the unselected bit linesduring the reading actions; apply the common unselect voltage to boththe unselected word lines and the unselected bit lines during theprogramming action; and apply the common unselect voltage to both theunselected word lines and the unselected bit lines during the erasingaction, and wherein the common unselected voltage has an absolute valuegreater than zero.
 54. The memory device of claim 53, wherein thevoltage switch circuit is further configured to apply the commonunselect voltage to at least the unselected word lines and theunselected bit lines during action preparing periods prior to thereading action, the programming action, and the erasing action.
 55. Thememory device of claim 53, further comprising: a memory cell selectingcircuit configured to select the selected memory cell from the memorycell array by row or column; and a reading circuit configured to readinformation stored in the selected memory cell by detecting an amount ofa reading current flowing according to a resistance value of a variableresistance element in the selected memory cell.
 56. The memory device ofclaim 53, wherein the voltage switch circuit is further configured toapply the common unselect voltage to one of the selected word line orthe selected bit line and to both of the unselected word line and theunselected bit line and apply a first reading voltage different from thecommon unselected voltage to the other of the selected word line or theselected bit line during the reading action.
 57. The memory device ofclaim 53, wherein the voltage switch circuit is further configured toapply a first programming voltage higher than the common unselectvoltage to one of the selected word line or the selected bit line andapply a second programming voltage lower than the common unselectvoltage to the other of the selected word line or the selected bit lineduring the programming action.
 58. The memory device of claim 53,wherein the voltage switch circuit is further configured to apply afirst erasing voltage higher than the common unselect voltage to one ofthe selected word line or the selected bit line and apply a seconderasing voltage lower than the common unselect voltage to the other ofthe selected word line or the selected bit line during the erasingaction.
 59. The memory device of claim 53, wherein a voltage applied tothe selected word line or the selected bit line during both of theprogramming and erasing actions is the ground voltage, and wherein thecommon unselect voltage is half or less of a programming voltage for theprogramming action for the variable resistance element or an erasingvoltage for the erasing action for the variable resistance element. 60.The memory device of claim 53, wherein a polarity of a first voltageapplied to the selected word line and the selected bit line is positiveand a polarity of a second voltage applied to the selected word line andthe selected bit line is negative during both of the programming anderasing actions.
 61. The memory device of claim 53, wherein the voltageswitch circuit is further configured to apply the common unselectvoltage to the selected word line, the selected bit line, the unselectedword lines, and the unselected bit lines in a standby state in whichnone of the reading action, the programming action, or the erasingaction is performed.
 62. A memory device comprising: a memory cell arrayincluding memory cells, wherein a first terminal of each memory cell ina same row is connected to a common word line, and wherein a secondterminal of each memory cell in a same column is connected to a commonbit line; and a voltage switch circuit configured to apply a voltage foreach of a plurality of memory actions to a selected word line and aselected bit line connected to a selected memory cell and to un-selectedword lines and unselected bit lines according to the plurality of memoryactions, wherein the plurality of memory actions include a readingaction and a programming action in the selected memory cell; wherein thevoltage switch circuit is further configured to: apply a common unselectvoltage to the unselected word lines during the reading actions and theprogramming actions and apply the common unselect voltage to theunselected bit lines during the reading actions and the erasing actions;or apply the common unselect voltage to the unselected bit lines duringthe reading actions and the programming actions and apply the commonunselect voltage to the unselected word lines during the reading actionsand the erasing actions, wherein the common unselect voltage has anabsolute value greater than zero.
 63. The memory device of claim 62,wherein the memory cells comprise a variable resistance element having aresistance value configured to reversibly change in response to electricpulse application.
 64. The memory device of claim 63, furthercomprising: a memory cell selecting circuit configured to select theselected memory cell from the memory cell array by row or column; and areading circuit configured to read information stored in the selectedmemory cell by detecting an amount of a reading current flowingaccording to a resistance value of the variable resistance element inthe selected memory cell.
 65. The memory device of claim 63, wherein thevariable resistance element comprises resistance random access memory,and wherein the voltage switch circuit is further configured to applythe common unselect voltage to the other of the unselected word linesand the unselected bit lines at least during the both the reading actionand the erasing action.
 66. The memory device of claim 62, wherein theplurality of memory actions further include an erasing action.
 67. Amemory device comprising: a memory cell array including memory cells,wherein a first terminal of each memory cell in a same row is connectedto a common word line, and wherein a second terminal of each memory cellin a same column is connected to a common bit line; and a voltage switchcircuit configured to apply a voltage for each of a plurality of memoryactions to a selected word line and a selected bit line connected to aselected memory cell and to unselected word lines and unselected bitlines according to the plurality of memory actions, wherein theplurality of memory actions include a reading action and a programmingaction in the selected memory cell; wherein the voltage switch circuitis further configured to: apply a common unselect voltage to both theunselected word lines and the unselected bit lines during the readingactions; and apply the common unselect voltage to both the unselectedword lines and the unselected bit lines during the programming action,and wherein the unselected voltage has an absolute value greater thanzero.
 68. The nonvolatile semiconductor memory device according to claim1, wherein the common unselect voltage is the same during each of thereading, programming, and erasing actions.